Although many materials have been considered for use in modern day semiconductor devices, silicon is presently used in the overwhelming majority of such devices. This is true even though other materials, such as Group III-V compound semiconductors, are potentially more promising than silicon for certain applications such as high speed field effect transistors. One Group III-V material, GaAs, has been rather extensively investigated for field effect transistor applications because such devices fabricated from this material are potentially faster than are silicon devices due to the higher drift mobility for electrons in GaAs.
Other materials, for example, Ga.sub.0.47 In.sub.0.53 As, are potentially more attractive FET applications than GaAs because they have still higher low electric field mobilities and can be grown lattice matched to InP substrates. This composition, as well as others containing phosphorus, is also of interest because it can be epitaxially grown lattice matched to InP substrates. However, the development of InGaAs field effect transistors has not progressed to the stage of development of GaAs FETs and of commercial devices at least partially because of the lack of a suitable gate structure. It is reported in, for example, Applied Physics Letters, 23, pp. 458-459, Oct. 15, 1973, a plain Au/Ga.sub.0.47 In.sub.0.53 As contact has a barrier height of approximately 0.2 volts and this height is too low for useful field effect transistor applications.
Several approaches have been taken in attempts to overcome the lack of suitable gate structure. Leheny et al. reported in IEEE Electron Device Letters, 1, pp. 110-111, June, 1980, an InGaAs junction field effect transistor with a p-n junction gate fabricated by Zn diffusion. While this device did have the advantage of a reduced gate leakage current because of the reverse biased p-n junction, such devices were not easily fabricated with short channel lengths. Morgan et al. reported in Electronics Letters, 14, pp. 737-738, Nov. 9, 1978, an InGaAs Schottky diode with barrier height of approximately 0.5 volts with the increase being due to the presence of a thin SiO.sub.x layer. While the presence of the SiO.sub.x layer did increase the apparent barrier height, it was undesirable because of the presence of a large number of trapping levels which could lead to charge storage effects. Additionally, GaInAs FETs using a semi-insulating Al.sub.0.48 In.sub.0.58 As layer to raise the Schottky barrier height were reported by Ohno et al. in IEEE Electron Device Letters, 1, pp. 154-155, August, 1980. The minimum thickness for the AlInAs layer that was required to prevent a substantial tunneling current was reported to be 200 Angstroms. This leads to an appreciable voltage drop across the insulating layer.
There are other reports in the literature of attempts to raise Schottky barrier heights on materials other than GaInAs. For example, Bucher, et al. reported in Applied Physics Letters, 23, pp. 617-619, Dec. 1, 1973 that Cu-diffused Au/CdS junctions had an increased Schottky barrier height. Shannon reported in Applied Physics Letters, 25, pp. 75-77, July 1, 1974, that the Schottky barrier height of Ni--Si diodes was increased by using ion implantation to create a shallow n-type layer on an underlying p-type layer.